ADAU1978WBCPZ-RL NAVN
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ADAU1978WBCPZ-RL ADI
Four 2 V rms differential inputs On-chip phase-locked loop (PLL) for master clock Low electromagnetic interference (EMI) design 109 dB analog-to-digital converter (ADC) dynamic range Total harmonic distortion + noise (THD + N): −95 dB Selectable digital high-pass filter 24-bit stereo ADC with 8 kHz to 192 kHz sample rates Digital volume control with autoramp function I 2C/SPI controllable for flexibility Software-controllable clickless mute Software power-down Right justified, left justified, I2S, and TDM modes Master and slave operation modes 40-lead LFCSP package Qualified for automotive applications
Four 2 V rms differential inputs On-chip phase-locked loop (PLL) for master clock Low electromagnetic interference (EMI) design 109 dB analog-to-digital converter (ADC) dynamic range Total harmonic distortion + noise (THD + N): −95 dB Selectable digital high-pass filter 24-bit stereo ADC with 8 kHz to 192 kHz sample rates Digital volume control with autoramp function I 2C/SPI controllable for flexibility Software-controllable clickless mute Software power-down Right justified, left justified, I2S, and TDM modes Master and slave operation modes 40-lead LFCSP package Qualified for automotive applications
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